General
Description
The 8 pin single PFC
controller with 50% PWM clock , CM6503/4 is a space-saving controller
for power factor corrected, switched mode power supplies that
offers very low start-up and operating currents. For the power
supply less than 500Watt, its performance could be very close
to CM6800 or ML4800 architecture. Its IAC has dual function. 8
pin CM6503/4 does not require and bleed resistors. It use IAC
pin during the start up condition to start up CM6503/4. After
CM6503/4 is on, IAC will switch itself back to the IAC function.
Power Factor Correction
(PFC) offers the use of smaller, lower cost bulk capacitors, reduces
power line loading and stress on the switching FETs, and results
in a power supply fully compliant to IEC1000-3-2 specifications.
The CM6503/4 includes circuits for the implementation of a leading
edge, average current "boost" type PFC and a trailing edge, PWM
Clock signal which will not turn on until PFC boost output reaches
steady state.
The CM6503's PFC and
PWM Clock operate at the same frequency, 67kHz. The PFC frequency
of the CM6504 is automatically set at half that of the 134kHz
PWM. This higher frequency allows the user to design with smaller
PWM components while maintaining the optimum operating frequency
for the PFC. An PFC OVP comparator shuts down the PFC section
in the event of a sudden decrease in load. The PFC section also
includes peak current limiting for enhanced system reliability.
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Features
- Enable lowest BOM
for power supply with PFC
- Patented slew rate
enhanced voltage error amplifier with advanced input current
shaping technique
- Universal Line
Input Voltage
- No bleed resistor
required
- CCM boost or DCM
boost with leading edge modulation PFC using Input Current Shaping
Technique
- Feedforward IAC
pin to do the automatic slope compensation
- PFCOVP, TriFault
Detect, PFC VCCOVP, Precision -1V PFC ILIMIT
- Low supply currents;
start-up: 100uA typical, operating current: 2mA typical
- Synchronized leading
PFC and trailing edge modulation PWM Clock for the down stream
DC to DC stage to reduce ripple current in the storage capacitor
between the PFC and PWM sections and to reduce switching noise
in the system
- VINOK Comparator
to guarantee to enable PWM Clock when PFC reach steady state
- UVLO, REFOK, and
brownout protection